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HDD32M72D9RPW
DDR SDRAM Module 256Mbyte (32Mx72bit), based on 32Mx8, 4Banks 8K Ref., 184Pin-DIMM with PLL & Register
Part No. HDD32M72D9RPW
GENERAL DESCRIPTION
The HDD32M72D9RPW is a 32M x 72 bit Double Data Rate(DDR) Synchronous Dynamic RAM high-density memory module. The module consists of nine CMOS 32M x 8 bit with 4banks DDR SDRAMs in 66pin TSOP-II 400mil packages and 2K EEPROM in 8-pin TSSOP package on a 184-pin glass-epoxy. Four 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each DDR SDRAM. The HDD32M72D9RPW is a DIMM(Dual in line Memory Module) .Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allows the same device to be useful for a variety of high bandwidth, high performance memory sy stem applications. All module components may be powered from a single 2.5V DC power supply and all inputs and outputs are SSTL_2 compatible.
FEATURES
* Part Identification
HDD32M72D9RPW - 10A HDD32M72D9RPW - 13A HDD32M72D9RPW - 13B : : : 100MHz (CL=2) 133MHz (CL=2) 133MHz (CL=2.5)
* 2.5V 0.2V VDD and VDDQ power supply * Double-data-rate architecture; two data transfers per clock cycle * Bidirectional data strobe(DQS) * Differential clock inputs(CK and /CK) * DLL aligns DQ and DQS transition with CK transition * Programmable Read latency 2, 2.5 (clock) * Programmable Burst length (2, 4, 8) * Programmable Burst type (sequential & interleave) * Edge aligned data output, center aligned data input * Auto & Self refresh, 7.8us refresh interval (8K/64ms refresh) * The used device is 8M x 8bit x 4Banks DDR SDRAM
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PIN ASSIGNMENT
PIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
HDD32M72D9RPW
Front
VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC /RESET VSS DQ8 DQ9 DQS1 VDDQ * CK1 * /CK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 53 54 55 56 57 58 59 60 61
PIN
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
Back
A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 CB0 CB1 VDD DQS8 A0 CB2 VSS CB3 BA1 KEY DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40
PIN
62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92
Frontl
VDDQ /WE DQ41 /CAS VSS DQS5 DQ42 DQ43 VDD * /CS2 DQ48 DQ49 VSS * CK2 * /CK2 VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL
PIN
93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123
Back
VSS DQ4 DQ5 VDDQ DM0 DQ6 DQ7 VSS NC NC *A13 VDDQ DQ12 DQ13 DM1 VDD DQ14 DQ15 CKE1 VDDQ * BA2 DQ20 A12 VSS DQ21 A11 DM2 VDD DQ22 A8 DQ23
PIN
124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
Front
VSS A6 DQ28 DQ29 VDDQ DM3 A3 DQ30 VSS DQ31 CB4 CB5 VDDQ CK0 /CK0 VSS DM8 A10 CB6 VDDQ CB7 KEY
PIN
154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184
Back
/RAS DQ45 VDDQ /CS0 /CS1 DM5 VSS DQ46 DQ47 * /CS3 VDDQ DQ52 DQ53 NC VDD DM6 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD
145 146 147 148 149 150 151 152 153
VSS DQ36 DQ37 VDD DM4 DQ38 DQ39 VSS DQ44
*These pins should be NC in the system which does not support SPD PIN PIN DESCRIPTION PIN A0~A12 BA0~BA1 DQ0~DQ63 CB0~CB7 DQS0~DQS7 DM0~DM7 CK0~CK2,/CK0~/CK2 CKE0 /CS0 /RAS /CAS /RESET
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PIN DESCRIPTION Power supply(2.5V) Power supply for DQs(2.5V) Power supply for reference Serial EEPROM Power supply(3.3) Ground Address in EEPROM Serial data I/O Serial clock Write protection VDD identification flag No connection
Address input Bank Select Address Data input/output Check bit(Data input/output) Data Strobe input/output Data-in Mask Clock input Clock enable input Chip Select input Row Address strobe Column Address strobe Reset Enable
2
VDD VDDQ VREF VSPD VSS SA0~SA2 SDA SCL WP VDDIN NC
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FUNCTIONAL BLOCK DIAGRAM
HDD32M72D9RPW
A0~A12
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PIN FUNCTION DESCRIPTION
Pin CK, /CK Clock Name
HDD32M72D9RPW
Input Function CK and /CK are differential clock inputs. All address and control input signals are sampled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to both edges of CK. Internal clock signals are derived from CK/CK. CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN(row ACTIVE in any bank). CKE is synchronous for all functions except for disabling outputs, which is achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled during power-down and self refresh modes, providing low standby power. CKE will recognize an LVCMOS LOW level prior to VREF being stable on power-up. /CS enables(registered LOW) and disables(registered HIGH) the command decoder. All commands are masked when /CS is registered HIGH. /CS provides for external bank selection on systems with multiple banks. /CS is considered part of the command code. Row/column addresses are multiplexed on the same pins.
CKE
Clock Enable
/CS
Chip Select
A0 ~ A12 BA0 ~ BA1 /RAS /CAS /WE DQS0 ~ 7
Address Bank select address Row address strobe Columnaddress strobe Write enable Data Strobe
Row address : RA0 ~ RA12, Column address : CA0 ~ CA9 BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-CHARGE command is being applied. Latches row addresses on the positive going edge of the CLK with /RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with /CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from /CAS, /WE active. Output with read data, input with write data. Edge -aligned with read data, centered in write data. Used to capture write data. DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled
DM0~7
Input Data Mask
on both edges of DQS. DM pins include dummy loading internally, to matches the DQ and DQS load-ing.
DQ0 ~ 63
Data input/output
Data inputs/outputs are multiplexed on the same pins. WP pin is connected to Vcc.
WP
Write Protection
When WP is " high" EEPROM Programming will be inhibited and the entire , memory will be write-protected.
VDDQ VDD VSS VREF
Supply Supply Supply Supply
DQ Power Supply : +2.5V 0.2V. Power Supply : +2.5V 0.2V (device specific). DQ Ground. SSTL_2 reference voltage.
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ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage on any pin relative to Vss Voltage on V DD supply relative to Vss Voltage on V DDQ supply relative to Vss Storage temperature Power dissipation SYMBOL VIN, VOUT VDD VDDQ TSTG PD
HDD32M72D9RPW
RATING -0.5 ~ 3.6 -1.0 ~ 3.6 -1.0 ~ 3.6 -55 ~ +150 13.5
UNTE V V V C W mA
Short circuit current IOS 50 Notes: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70 ) C)
PARAMETER Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage(system) Input High Voltage Input Low Voltage Input Voltage Level, CK and /CK inputs Input Differential Voltage, CK and /CK inputs Input leakage current Output leakage current Output High current (Normal strengh driver) ;VOUT = VTT + 0.84V Output Low current (Normal strengh driver) ;VOUT = VTT - 0.84V Output High current (Half strengh driver) ;VOUT = VTT + 0.45V Output Low current (Half strengh driver) ;VOUT = VTT - 0.45V SYMBOL VDD VDDQ VREF VTT VIH (DC) VIL (DC) VIN (DC) VID (DC) I LI I OZ I OH MIN 2.3 2.3
VDDQ/2-50mV
MAX 2.7 2.7
VDDQ/2+50mV
UNIT V V V V V V V V uA uA mA
NOTE
1 2
VREF - 0.04 VREF + 0.15 -0.3 -0.3 0.3 -2 -5 -16.8
VREF + 0.04 VREF + 0.3 VREF - 0.15 VDDQ + 0.3 VDDQ + 0.6 2 5
3
I OL
16.8
mA
IOH
-9
mA
IOL
9
mA
Notes 1. Includes 25mV margin for DC offset on VREF, and a combined total of 50mV margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of 3nH. 2. VTT is not applied directly to the device. V TT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ. 5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same. 6. These charactericteristics obey the SSTL-2 class II standards.
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INPUT/OUTPUT Capacitance
DESCRIPTION
HDD32M72D9RPW
(VDD = 2.5V, VDDQ = 2.5V, TA = 25 C, F = 1MHZ)
SYMBOL MIN MAX UNITS
Input Capacitance(A0 ~ A12, BA0 ~ BA1,/RAS,/CAS,/ WE ) Input Capacitance(CKE0) Input Capacitance( /CS0) Input Capacitance( CLK0,/CLK0 ) Data & DQS input/output Capacitance(DQ0~DQ63) Data input/output Capacitance(CB0~CB7) Input Capacitance(DM0~DM8)
CIN1 CIN2 CIN3 CIN4 COUT1 COUT2 CIN5
-
12 12 11 12
11 11 11
pF pF pF pF PF PF pF
AC Operating Conditions
PARAMETER/ Condition Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals. Input Differential Voltage, CK and CK inputs Input Crossing Point Voltage, CK and CK inputs STMBOL VIH (AC) VIL (AC) VID (AC) VIX (AC) 0.7 0.5*VDDQ-0.2 MIN VREF + 0.31 VREF - 0.31 VDDQ+0.6 0.5*VDDQ+0.2 V V V MAX UNIT NOTE 3 3 1 2
Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of V IX is expected to equal 0.5* VDDQ of the transmitting device and must track variations in the DC level of the same. 3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simulation. the AC and DC input specificatims are refation to a V REF envelope that has been bandwidth limited 20MHz.
AC Operating TEST Conditions
PARAMETER Input reference voltage for Clock Input signal maximum peak swing Input Levels(VIH/VIL) Input timing measurement reference level Output timing measurement reference level Output load condition VALUE 0.5 * VDDQ 1.5 VREF+0.31/VREF-0.31 VREF VTT See Load Circuit UNIT V V V V V V NOTE
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AC Timming Parameters & Specifications
PARAMETER Row cycle time Refresh row cycle time Row active time /RAS to /CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Col. address to Col. address delay Clock cycle time CL=2.0 CL=2.5 SYMBOL tRC tRFC tRAS tRCD tRP tRRD tWR tCDLR tCCD tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tHZQ tDQSS tWPRES tWPREH tDSS tDSH tDQSH tDQSL tDSC tIS tIH tMRD tDS tDH tDIPW tPDEX tXSW tXSA tXSR tREF tWPST 70 80 48 20 20 15 15 1 1 10 0.45 0.45 -0.8 -0.8 0.9 0.4 -0.8 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 1.1 1.1 16 0.6 0.6 2 10 116 80 200 7.8 0.4 0.6 1.1 12 0.55 0.55 +0.8 +0.8 +0.6 1.1 0.6 +0.8 1.25 120K
HDD32M72D9RPW
(These AC charicteristics were tested on the Component) DDR200 -10A MIN MAX MIN 65 75 45 20 20 15 15 1 1 7.5 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 -0.75 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 15 0.5 0.5 1.75 7.5 95 75 200 7.8 0.4 0.6 75 200 7.8 0.4 0.6 1.1 12 12 0.55 0.55 +0.75 +0.75 +0.5 1.1 0.6 +0.75 1.25 120K DDR266A -13A MAX 65 75 45 20 20 15 15 1 1 10 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 -0.75 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 15 0.5 0.5 1.75 7.5 1.1 12 12 0.55 0.55 +0.75 +0.75 +0.5 1.1 0.6 +0.75 1.25 120K DDR266B -13B MIN MAX ns ns ns ns ns ns tCK tCK tCK ns ns tCK tCK ns ns ns tCK tCK ns tCK ns tCK tCK tCK tCK tCK tCK ns ns ns ns ns ns ns ns ns Cycle us tCK 1 3 6 6 3 2 5 5 5 1 1,2 1,2 3 3 3 3 2
UNIT NOTE
Clock high level width Clock low level width DQS-out access time from CK/CK Output data access time from CK/CK Data strobe edge to ouput data edge Read Preamble Read Postamble Data out high impedence time from CK -/CK CK to valid DQS-in DQS-in setup time DQS-in hold time DQS-in falling edge to CK rising-setup time DQS-in falling edge to CK rising hold time DQS-in high level width DQS-in low level width DQS-in cycle time Address and Control Input setup time Address and Control Input hold time Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS DQ & DM input pulse width Power down exit time Exit self refresh to write command Exit self refresh to bank active command Exit self refresh to read command Refresh interval time DQS write postamble time
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Notes :
1. 2. Maximum burst refresh cycle : 8
HDD32M72D9RPW
The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. A write command can be applied with tRCD satisfied after this command. For registered DIMMs, tCL and tCH are 45% of the period including both the half period jitter (tJIT(HP) ) of the PLL and the half jitter due to crosstalk (tJIT(crosstalk) ) on the DIMM. Input Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate (V/ns) 0.5 0.4 tIS (ps) 0 +50 tIH (ps) 0 +50
3. 4. 5. 6.
-
0.3 +100 +100 This derating table is used to increase tDS/tDH in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 7. I/O Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate (V/ns) 0.5 0.4 tIS (ps) 0 +75 tIH (ps) 0 +75
-
0.3 +150 +150 This derating table is used to increase tDS/tDH in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 8. I/O Setup/Hold Plateau Derating I/O Input Level (mV) tDS (ps) tDH (ps)
-
280 +50 +50 This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF 310mV for a duration of up to 2ns. 9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating Delta Rise/Fall Rate (ns/V) 0 0.25 tDS (ps) 0 +50 tDH (ps) 0 +50
-
0.5 +100 +100 This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall Rate =0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate. 10. This parameter is fir system simulation purpose. It is guranteed by design. 11. For each of the terms, if not already an integer, round to the next highest integer. t CK is actual to the system clock cycle time.
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HDD32M72D9RPW
COMMAND TRUTH TABLE (V=Valid, X=Don't Care, H=Logic High, L=Logic Low)
COMMAND CK E n-1 CKE n /CS /RAS /CAS /WE DM BA 0,1 A10/ AP A11 A9~A0 NOTE
Register Register
Extended MRS Mode register set Auto refresh Entry Exit
H H H L H
X X H L H X
L L L L H L
L L L H X L
L L L H X H
L L H H X H
X X X X X V
OP code OP code X X Row address L Column Address H L (A0 ~ A9) Column Address H (A0 ~ A9) X V X L H X X
1,2 1,2 3 3 3 3
Refresh
Self refresh
Bank active & Row Addr. Read & column address Write & column address Auto precharge disable Auto precharge eable Auto precharge disable Auto precharge enable Burst Stop Precharge Bank selection All banks Entry Exit Entry Exit
4 4 4 4,6 7 5
H
X
L
H
L
H
X
V
H
X
L
H
L
L
X
V
H H H L H L H H
X X L H L H
L L H L X H L H L H L
H L X V X X H X V X X H
H H X V X X H X V X H
L L X V X X H X V X H
X X X X X
Clock suspend or active power down
Precharge power down mode DM
X X V X X X 8
No operation command Note :
1. 2. 3.
X
OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. Burst stop command is valid at every burst length. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM. 9 HANBit Electronics Co.,Ltd.
4.
5. 6.
7. 8. 9.
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PACKAGE DIMENSIONS
Unit : mm
HDD32M72D9RPW
< Front -Side >
133.35 0.20
30.48 0.20
< Rear -Side >
133.35 0.20
30.48 0.20
ORDERING INFORMATION
Part Number HDD32M72D9RPW-10A HDD32M72D9RPW-13A HDD32M72D9RPW-13B Density 256MByte 256MByte 256MByte Org. 32M x 72 32M x 72 32M x 72 Package 184PIN DIMM 184PIN DIMM 184PIN DIMM Ref. 8K 8K 8K Vcc 2.5V 2.5V 2.5V MODE DDR DDR DDR MAX.frq 100MHz/CL2 133MHz/CL2 133MHz/CL2.5
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